`include "define.v"

module if_id (
    input wire rst,
    input wire clk,
    input wire[`InstAddrBus] if_pc,
    input wire[`InstBus] if_inst,
    input wire[`StallBus] if_stall,
    input wire            flush,
    output reg[`InstAddrBus] id_pc,
    output reg[`InstBus] id_inst
);
    
    always @(posedge clk) begin
        if (rst == `RstEnable) begin
            id_pc <= `ZeroWord;
            id_inst <= `ZeroWord;
        end else begin
            if (flush == 1'b1) begin
                id_pc <= `ZeroWord;
                id_inst <= `ZeroWord;
            end else if (if_stall[`STALL_IF] == `NoStop) begin
                id_pc <= if_pc;
                id_inst <= if_inst;
            end else if(if_stall[`STALL_IF] == `Stop && if_stall[2] == `STALL_ID) begin
                id_pc <= `ZeroWord;
                id_inst <= `ZeroWord;
            end
        end
    end

endmodule